In a conventional art, operation processing apparatuses have been embodied using hardware or software. For example, when a network controller for performing as a network interface is installed on a computer chip, the network controller performs only a network interfacing function that is defined during its fabrication in a factory. Therefore, after fabrication of the network controller, it may not be possible to change the function of the network controller. This is an example of a hardware embodiment scheme. Another scheme uses software. For example, a user's intention may be satisfied by a program to perform the user's desired functions and executing the program in a general purpose processor. A software embodiment scheme enables a new function to be performed by replacing only software even after hardware was fabricated in the factory. When using software, it is possible to perform various types of functions using the given hardware, however, execution speed decreases in comparison to the hardware embodiment scheme.
In order to overcome the above-described disadvantages of the hardware and software schemes, a reconfigurable processor architecture was proposed. The reconfigurable processor architecture may be customized to solve a given problem even after device fabrication. Also, the reconfigurable processor architecture may use a spatially customized calculation to perform calculations.
The reconfigurable processor architecture may be embodied by using a coarse-grained array (CGA) and a processor core that can process a plurality of instructions in parallel.
A general processor uses a cache to more effectively use a memory. The cache is installed between the processor and a main memory, is smaller than the main memory, and can operate more quickly than the main memory.
Elements affecting the performance of a cache memory system include a cache hit ratio, a data access time in a cache hit state, a penalty in the case where a cache miss occurs, and the like.
Accordingly, there is a need for a method to reduce a cache miss when operating a reconfigurable processor in a processor core mode, and a processor, having a CGA mode and a processor core mode, using the method.